1. Field
This patent document relates to a memory device, a memory system, and a method for operating a memory device.
2. Description of the Related Art
The semiconductor memory device market continues demand higher integration, higher capacity and higher operation speeds. This new generation of semiconductor memory devices is highly integrated and has multiple memory blocks that may independently transmit and receive command signals, addresses and data. Additionally, this new generation of semiconductor memory devices has multiple facets integrated in a single semiconductor memory device.
FIG. 1 is a configuration diagram of a semiconductor memory device 100 including a plurality of memory blocks 110_0 to 110_N.
The semiconductor memory device 100 includes a plurality of channels CH_0 to CH_N which respectively correspond to the plurality of memory blocks 110_0 to 110_N. The plurality of memory blocks 110_0 to 110_N may receive command signals and addresses and may receive and transmit data, from and to an exterior of the semiconductor memory device 100 through corresponding channels among the plurality of channels CH_0 to CH_N. For reference, each of the plurality of channels CH_0 to CH_N includes a plurality of lines for transferring signals.
After the semiconductor memory device 100 is fabricated, it is necessary to perform a test to check whether the semiconductor memory device 100 operates properly. In order to perform the test, it is necessary to apply signals to the plurality of memory blocks 110_0 to 110_N included in the semiconductor memory device 100 and thereby operate the memory blocks 110_0 to 110_N. In order to separately apply testing signals to the respective memory blocks 110_0 to 110_N from the exterior (for example, test equipment), signal input/output ports are needed in numbers equal to the plurality of channels CH_0 to CH_N included in the semiconductor memory device 100.
Since test equipment has a limited number of signal input/output ports, the number of semiconductor memory devices which may be tested at a time by the test equipment decreases when the number of ports needed to test one memory device increases. As a consequence, time and cost required to perform a test may increase.